library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;

library work;
    use work.router_pack.all;
    use work.env_pack.all;

-------------------------------------------------------------------------
    
entity collector is
     
port(
    -- General Signals: --
    RESET           		: in std_logic;
    CLK             		: in std_logic;
    CYCLE_COUNTER   	: in std_logic_vector(e_cycle_counter_width_c-1 downto 0);
    MODULE_ID		: in std_logic_vector(2*e_coord_position_width_c-1 downto 0);
    
    -- Input Port i/f: --
    RI      : in std_logic;
    AI      : out std_logic;
    DI      : in std_logic_vector(flit_size_c-1 downto 0)
);    
    
end collector;

-------------------------------------------------------------------------

architecture collector_arch of collector is

-- Collector Components --

component collector_if
port(
    -- General Signals: --
    RESET   : in std_logic;
    CLK     	: in std_logic;
    
    -- Input Port i/f: --
    RI      : in std_logic;
    AI      : out std_logic;
    DI      : in std_logic_vector(flit_size_c-1 downto 0);
    
    -- Packet Output --
    PACKET_RECEIVED 	: out std_logic;
    SL              		: out std_logic_vector(msl_ind_width-1 downto 0);
    PACKET_SIZE     	: out std_logic_vector(e_packet_size_width_c-1 downto 0);
    PACKET_ID       	: out std_logic_vector(e_packet_id_width_c-1 downto 0)
);
end component;

component loger
port(    
    -- General Signals: --
    RESET          		: in std_logic;
    CLK            		: in std_logic;
    CYCLE_COUNTER   	: in std_logic_vector(e_cycle_counter_width_c-1 downto 0);
    MODULE_ID		: in std_logic_vector(2*e_coord_position_width_c-1 downto 0);
    LOGER_TYPE		: in std_logic;
    
    -- Packet Info: --
    VALID           		: in std_logic;
    SL              		: in std_logic_vector(msl_ind_width-1 downto 0);
    PACKET_SIZE     	: in std_logic_vector(e_packet_size_width_c-1 downto 0);
    PACKET_ID       	: in std_logic_vector(e_packet_id_width_c-1 downto 0)
);
end component;

-- Internal Signals
signal packet_received  : std_logic;
signal sl                	: std_logic_vector(msl_ind_width-1 downto 0);
signal packet_size       	: std_logic_vector(e_packet_size_width_c-1 downto 0);
signal packet_id         	: std_logic_vector(e_packet_id_width_c-1 downto 0);
signal loger_type		: std_logic;

-- Collector Implementation --

begin
   
   u_collector_if: collector_if
   port map(
      RESET             => RESET,
      CLK               => CLK,
      
      RI                => RI,
      AI                => AI,
      DI                => DI,
      
      PACKET_RECEIVED  => packet_received,
      SL			=> sl,
      PACKET_SIZE	=> packet_size,
      PACKET_ID         	=> packet_id
    );
    
    u_loger: loger
    port map(
        RESET          	=> RESET,
        CLK            	=> CLK,
        CYCLE_COUNTER	  => CYCLE_COUNTER,
        MODULE_ID		     => MODULE_ID,
	     LOGER_TYPE	     => loger_type,
        VALID          	=> packet_received,
        SL             	=> SL,
        PACKET_SIZE    	=> PACKET_SIZE,
        PACKET_ID      	=> PACKET_ID
    );
   
   -- Internal signals assignment
   loger_type <= loger_type_collector;
   
end collector_arch;

-------------------------------------------------------------------------

configuration collector_cfg of collector is
    for collector_arch
    end for;
end collector_cfg;
